1. Field of the Invention
The present invention relates generally to a semiconductor device and a method for fabricating the semiconductor device, and relates, for example, to a MOS transistor using SiGe for a substrate.
2. Description of the Related Art
Conventionally, there is known a MOS transistor in which a source region and a drain region are formed by SiGe, as disclosed, for instance, in Jpn. Pat. Appln. KOKAI Publication No. 2005-142431.
In this type of transistor, an epitaxial SiGe is grown on the recessed source/drain region while gate-electrode is covered with hard mask, e.g. SiN, so that SiGe will not grow on it. In this structure, as the depth of the recessed regions increases, a higher compressive stress is induced in a channel region. Thus, the hole mobility of the MOS transistor can be improved.
However, when the source/drain regions are being recessed, there may occur a case in which the hard mask on the gate electrode is eroded and stripped away by the source/drain recess. Consequently, SiGe may grow also on the gate electrode, and this will cause the electrical connection between neighboring MOS transistors. Further, the source/drain and the gate electrode also may be shorted. It is thus difficult to recess into the source/drain region deeply, i.e. the epitaxially grown SiGe layers, and it is hard to further enhance the performance of the MOS transistor.